A Concurrent Testing Method for NoC Switches

Provided by: edaa
Topic: Hardware
Format: PDF
This paper proposes reuse of on-chip networks for testing switches in Network on Chips (NoCs). The proposed algorithm broadcasts test vectors of switches through the on-chip networks and detects faults by comparing output responses of switches with each other. This algorithm alleviates the need for: external comparison of the output response of the circuit-under-test with the response of a fault free circuit stored on a tester, on-chip signature analysis and a dedicated test-bus to reach test vectors and collect their responses. Experimental results on a few test benches compare the proposed algorithm with traditional System on Chip (SoC) test methods.

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