A Cross-Layer Approach for New Reliability-Performance Trade-Offs in MLC NAND Flash Memories

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Provided by: edaa
Topic: Storage
Format: PDF
In spite of the mature cell structure, the memory controller architecture of Multi-Level Cell (MLC) NAND flash memories is evolving fast in an attempt to improve the Uncorrected/miscorrected Bit Error Rate (UBER) and to provide a more flexible usage model where the performance-reliability trade-off point can be adjusted at runtime. However, optimization techniques in the memory controller architecture cannot avoid a strict trade-off between UBER and read throughput. In this paper, the authors show that co-optimizing ECC architecture configuration in the memory controller with program algorithm selection at the technology layer, a more flexible memory sub-system arises, which is capable of unprecedented trade-offs points between performance and reliability.
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