Systolic array is known as an architecture that can process a large amount of data with high speed, by large scale parallel and pipeline processing. If dynamic reconfiguration of systolic array is realized, flexible circuit construction and reduction of circuit scale become possible, without sacrificing the processing speed. Therefore, this paper proposes architecture of Dynamically Reconfigurable Systolic Array (DRSA). The circuit has been designed by using VHDL, and verified with a logic circuit simulator. The calculations of matrix such as 1-by-64 and 8-by-8 were simulated correctly using a lot of PEs (Processing Element).