A Design Comparison of Low Power 50 nm Technology Based Inverter With Sleep Transistor and MTCMOS Scheme
In this paper, the authors proposes a sleep transistor based minimum size inverter in BSIM4.3.0, 50nm CMOS technology with supply voltage of 1V, power dissipation of 46.28nW at 0.502V and maximum drain current of 70nA. The operating frequency is kept at 1GHz, and found that it can be used up to 10GHz successfully. The reduction in power dissipation is 98.88% and operating frequency is almost 2 times that of classical CMOS inverter. It is also found better than MTCMOS in terms of delay and maximum power delay product.