A Design Flow for Configurable Embedded Processors Based on Optimized Instruction Set Extension Synthesis

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Provided by: edaa
Topic: Hardware
Format: PDF
Design tools for Application Specific Instruction set Processors (ASIPs) are an important discipline in system-level design for wireless communications and other embedded application areas. Some ASIPs are still designed completely from scratch to meet extreme efficiency demands. However, there is also a trend towards use of partially predefined, configurable RISC-like embedded processor cores that can be quickly tuned to given applications by means of Instruction Set Extension (ISE) techniques. While the problem of optimized ISE synthesis has been studied well from a theoretical perspective, there are still few approaches to an overall HW/SW design flow for configurable cores that take all real-life constraints into account.
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