A Design Flow for Partially Reconfigurable Heterogeneous Multi-Processor Platforms

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Provided by: National University of Singapore
Topic: Hardware
Format: PDF
Modern Multi-Processor System-on-Chips (MPSoCs) are expected to handle multi-application use cases. As the number and complexity of these applications scale, resource allocation to meet the application throughput requirement is becoming quite a challenge. In this paper, a complete design flow is proposed for partially reconfigurable heterogeneous MPSoC platforms. The proposed flow determines the minimum resources required to map and guarantee the throughput of applications in all use-cases. Further, a suitable mapping for each application is chosen so that energy consumption is minimized.
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