International Journal of Latest Trends in Engineering and Technology (IJLTET)
Designing low power high-speed arithmetic circuit requires a combination of techniques at four levels; algorithm, architecture, circuit and system levels. Digital multipliers are the most commonly used components in many digital circuit designs. Most high performance DSP systems rely on hardware multiplication to achieve high data throughput. There are various types of multipliers available depending upon the application in which they are used. This paper focuses on an algorithm, called tree multiplication, which is suitable for high-speed and low-power applications. The algorithm is symmetric so it's very applicable for binary multiplication, due to the interchangeability of the multiplicand and the multiplier.