A Digital CMOS Parallel Counter Architecture

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Provided by: IRD India
Topic: Hardware
Format: PDF
In this paper, the authors consist of the state look-ahead path and the counting path. The proposed counter is a single mode counter, which sequences through a fixed set of pre assigned count states, of which each next count state represents the next counter value in sequence. The counter is partitioned into uniform 2-bit synchronous up counting modules. Next state transitions in counting modules of higher significance are enabled on the clock cycle preceding the state transition using stimulus from the state look-ahead path. Therefore, all counting modules concurrently transition to their next states at the rising clock edge.
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