International Journal of Research in Electronics and Computer Engineering (IJRECE)
Among many techniques of power reduction the technique of power gating is used considering the different modes of operation of flip-flop. In the proposed flip sleep mode and idle mode are used maintaining their state of data retention having pulse triggering on both edges rising and falling, of the clock. The circuit has used low threshold voltages so as to operate at low Vdd .The simulation of the circuit is done using tanner tool in 45nm technology. The comparison of the proposed circuit, when done with the DETFF1 and DETFF2 operated at 0.5V, the proposed latch has 72% power saving.