Association for Computing Machinery
In the past, the Spin-Transfer Torque RAM (STT-RAM) suffered from the slow write speed and the high write energy consumption. The latest progress in device engineering has dramatically reduced the right time to a few nanoseconds and hence enabled the Fast-Switching STT-RAM (FS-STT-RAM). However, the enhancement in write performance results in the degradation of read operations, in terms of both speed and data reliability. The authors' analysis shows that the read performance becomes critical. Based upon the tradeoff among the read latency, read errors, and system performance, they propose a new FS-STT-RAM architecture, which can switch between two operation modes for either high data accuracy or low power consumption with the support of operation system.