The University of Tulsa
Soft error rates in microprocessor logic have been projected to increase at an alarming rate. Soft errors can be handled at the process level, circuit level, or at the architecture level. Redundant Multi-Threading (RMT) has been proposed as an architectural approach that efficiently detects and recovers from soft errors. RMT can impose non-trivial overheads in terms of power consumption. In this paper, the authors characterize some of the major factors that influence the power consumed by RMT. They outline mechanisms that can reduce this power and derive simple analytical estimates to identify the most promising approach.