A Flexible DSP Block to Enhance FPGA Arithmetic Performance

Provided by: Ecole Polytechnique Federale de Lausanne
Topic: Hardware
Format: PDF
The authors propose a new DSP block for use in modern high-performance FPGAs. Current DSP blocks contain fixed bit-width multipliers that can be combined efficiently to form larger multipliers. Their approach is similar, but includes a bypass layer following the partial product generator that exposes the compressor tree used for partial product reduction directly to the user. As a consequence, the proposed DSP block can accelerate multi-input addition operations in addition to multiplication. To increase the flexibility of the device, the partial product reduction tree used within their DSP block uses a fixed function compression logic along with a Field Programmable Compressor Tree (FPCT), the latter of which is user-configurable to meet the needs of the application at hand.

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