A Floating-Point Accumulator for FPGA-Based High Performance Computing Applications

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Provided by: Iowa State University
Topic: Hardware
Format: PDF
A floating-point accumulator for FPGA-based high performance computing applications is proposed and evaluated. Compared to previous paper, their accumulator uses a fixed size circuit, and can reduce an arbitrary number of input sets of varying sizes without requiring prior knowledge of the bounds of summands. In this paper, they describe how the adder accumulator operator can be heavily pipelined to achieve a high clock speed when mapped to FPGA technology, while still maintaining the original input ordering.
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