National Technical University of Athens
Placement is an essential step in Electronic Design Automation (EDA). An inferior placement will not only affect the performance of digital applications mapped onto the FPGA, but might also make the circuit unroutable by producing excessive wirelength, which is beyond the available fabricated routing resources. Throughout this paper, the authors propose a novel placer, based on genetic algorithm, targeting to FPGAs. Rather than relevant approaches which are executed sequentially, the new placer exhibits inherent parallelism, which can be benefit from multi-core processors.