Institute of Electrical & Electronic Engineers
With increasing performance-per-watt implementation requirements for emerging applications and barriers in interconnect scaling for Ultra-Deep Sub-Micron (UDSM) technologies; traditional 2D-Integrated Circuits (2D-ICs) are being pushed to their limit. Three Dimensional-Integrated Circuits (3D-ICs) have recently emerged as a promising solution that can overcome many of the performance, area, and power concerns in 2D-ICs. In this paper, the authors propose a novel framework for the synthesis of application-specific 3D Networks-on-Chips (NoCs). The goal is to generate 3D NoCs that meet application performance constraints while minimizing power dissipation.