With sizes of MOS transistors scaling down, energy dissipation has become a major consideration concern in nanometer CMOS circuits. Near-threshold computing for CMOS circuits can respectively reduce both dynamic and leakage power dissipations. In this paper, a near-threshold full adder standard cell is developed and embedded into commercial standard-cell libraries. The full adder standard cell is optimized to achieve low Energy Delay Product (EDP). The layout, abstract design and standard-cell characters of near-threshold full adder are described. A 2-bit multiplier is verified with the proposed full adder standard cell by using commercial EDA tools.