A Fully Associative Cache Algorithm With Improved Performance

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Provided by: Journal of Theoretical and Applied Information Technology
Topic: Storage
Format: PDF
Fully associative caches enable all blocks to map address. This paper proposes an algorithm to enable one fully associative block. The address a is right shifted by certain prefixed number of bits. The result is XOR'ed with n-1, n being the number of fully associative cache blocks. The bit selection of the result to map to one of the n blocks in fully associative cache is performed. The chosen block is enabled to access a line or place cache line.
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