A Fully-Synthesizable Single-Cycle Interconnection Network for Shared-L1 Processor Clusters

Provided by: edaa
Topic: Hardware
Format: PDF
Shared L1 memory is an interesting architectural option for building tightly-coupled multi-core processor clusters. The authors designed a parametric, fully combinational Mesh-of-Trees (MoT) interconnection network to support high-performance, single-cycle communication between processors and memories in L1-coupled processor clusters. Their interconnect IP is described in synthesizable RTL and it is coupled with a design automation strategy mixing advanced synthesis and physical optimization to achieve optimal Delay, Power, Area (DPA) under a wide range of design constraints.

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