A Generic Traffic Model for On-Chip Interconnection Networks

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Provided by: University of Calgary
Topic: Hardware
Format: PDF
On-chip inter-connection networks or Network-on-Chips (NoCs) are becoming the de-facto scaling communication techniques in Multi-Processor System-on-Chip (MPSoC) or Chip Multi-Processor (CMP) environment. However, the current traffic models for on-chip inter-connection networks are insufficient to capture the traffic characteristics as well as evaluate the network performance. As the technology scaling enables the increase of available on-chip resources and innumerable new network architectures are proposed, there is a need to make NoCs more application-specific. Therefore, a traffic model to characterize such an application-specific network is necessary.
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