Institute of Electrical & Electronic Engineers
In the modern VLSI design flow, global router is often utilized to provide fast and accurate congestion analysis for upstream processes to improve the design routability. Global routing parallelization is a good candidate to speedup its runtime performance while delivering very competitive solution quality. In this paper, the authors study the cause of insufficient exploitable concurrency of the existing net level concurrency model, which has become a major bottleneck for parallelizing the emerging design problems. Then, they mitigate this limitation with a novel fine grain parallel model, with which a GPU based multi-agent global router is designed.