A Hardware-Efficient Architecture for Embedded Real- Time Cascaded Support Vector Machines Classification

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Provided by: Association for Computing Machinery
Topic: Hardware
Format: PDF
In this paper, the authors present an optimized architecture for cascaded SVM processing, along with a hardware reduction method for the implementation of the additional stages in the cascade, leading to significant improvements. The architecture was implemented on a Virtex 5 FPGA platform and evaluated using face detection as the target application on 640
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