A Hardware/Software Framework for Supporting Transactional Memory in a MPSoC Environment

Provided by: University of Bochum
Topic: Hardware
Format: PDF
Manufacturers are focusing on Multi-Processor System-on-Chip (MPSoC) architectures in order to provide increased concurrency, rather than increased clock speed, for both large-scale as well as embedded systems. Traditionally lock-based synchronization is provided to support concurrency; however, managing locks can be very difficult and error prone. In addition, the performance and power cost of lock-based synchronization can be high. Transactional memories have been extensively investigated as an alternative to lock-based synchronization in general-purpose systems. It has been shown that transactional memory has advantages over locks in terms of ease of programming, performance and energy consumption.

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