A High Bit Rate Serial-Serial Multiplier

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Provided by: IRD India
Topic: Hardware
Format: PDF
A design of serial-serial hybrid multiplier is proposed for applications with high data rate. Here the proposed technique effectively forms the entire partial product rows in just n cycles whereas conventional serial-serial multipliers take 2n cycles to form all partial products. The conventional way of partial product formation is rearranged here. Here the proposed architecture achieves high data rate by replacing full adders with asynchronous 1's counter so that critical path is limited to only DFF and an AND gate.
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