A High Level SoC Power Estimation Based on IP Modeling

Provided by: Institute of Electrical & Electronic Engineers
Topic: Hardware
Format: PDF
Current electronic system design requires being concerned with power consumption consideration. However, in a lot of design tools, the application power consumption budget is estimated after RTL synthesis. The authors propose in this paper a methodology based on measurements which allows modeling the application power consumption with architectural and algorithmic parameters. So, the modeled applications can be added in a library in order to help the system designer to determine early in the design flow the best adequacy between high performances and low power consumption.

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