A High Speed CMOS Image Sensor with a Novel Digital Correlated Double Sampling and a Differential Difference Amplifier

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Provided by: MDPI AG
Topic: Hardware
Format: PDF
In order to increase the operating speed of a CMOS Image Sensor (CIS), a new technique of digital Correlated Double Sampling (CDS) is described. In general, the Fixed Pattern Noise (FPN) of a CIS has been reduced with the subtraction algorithm between the reset signal and pixel signal. This is because a single-slope Analog-to-Digital Converter (ADC) has been normally adopted in the conventional digital CDS with the reset ramp and signal ramp. Thus, the operating speed of a digital CDS is much slower than that of an analog CDS.
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