International Journal of Computer Applications
Flip flops and latches form part of clock distribution network, timing elements, memory etc. in digital systems. This paper presents an efficient explicit pulsed static dual edge triggered flip flop with an improved performance. The proposed design overcomes the drawbacks of the dynamic logic family and uses explicit clock pulse generator approach to achieve dual edge triggering. The proposed flip-flop is compared with existing explicit pulsed dual edge triggered flip-flops. Based on the simulation results overall improvements of 12.67% and 10.15% are observed in delay and power delay product respectively.