A High-Speed Parallel Implementation of CCSDS LDPC Codec

Provided by: AICIT
Topic: Hardware
Format: PDF
Low-Density Parity-Check (LDPC) code is a linear block code with a sparse check matrix first introduced by the researcher, which was forgotten for a long time due to high implement complexity and lack of viable decoding algorithm, until an effective graphical representation called Tanner-graph was proposed by the researcher. QC-LDPC codes have been chosen by CCSDS for near-earth and deep-space applications. In this paper, an efficient high-speed parallel implementation of CCSDS LDPC codec is presented. SRAA circuits are used to complete the encoding computing, and min-sum algorithm is implemented with a parallel architecture on FPGA. The codec has a throughput of 2Gbps and good BER performance, taking only about 4M memory bits.

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