Provided by: Creative Commons
A digital clock rate multiplier, divisor using variable point math which generates the output clock with almost zero occurrence error has been presented. The circuit has an uncontrolled multiplication and division factor range and short lock time. A short power method has been incorporated to ensure that the overall power consumption of the circuit is low. The circuit has been premeditated in TSMC 65nm CMOS process for an input allusion time of 0.01ns and has been tested with indiscriminate multiplication factor values; the authors present a novel architecture to perform high speed multiplication using ancient Vedic math's techniques.