A Highly Resilient Routing Algorithm for Fault-Tolerant NoCs

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Provided by: edaa
Topic: Hardware
Format: PDF
Current trends in technology scaling foreshadow worsening transistor reliability as well as greater numbers of transistors in each system. The combination of these factors will soon make long-term product reliability extremely difficult in complex modern systems such as System-on-Chip (SoC) and Chip Multi-Processor (CMP) designs, where even a single device failure can cause fatal system errors. Resiliency to device failure will be a necessary condition at future technology nodes. In this paper, the authors present a Network-on-Chip (NoC) routing algorithm to boost the robustness in interconnect networks, by reconfiguring them to avoid faulty components while maintaining connectivity and correct operation.
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