A Hybrid Non-Volatile SRAM Cell with Concurrent SEU Detection and Correction

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Provided by: edaa
Topic: Storage
Format: PDF
In this paper the authors present a hybrid Non-Volatile (NV) SRAM cell with a new scheme for SEU tolerance. The proposed NVSRAM cell consists of a 6T SRAM core and a Resistive RAM (RRAM), made of a 1T and a Programmable Metallization Cell (PMC). The proposed cell has Concurrent Error Detection (CED) and correction capabilities; CED is accomplished using a dual-rail checker, while correction is accomplished by utilizing the restore operation; data from the non-volatile memory element is copied back to the SRAM core. The dual-rail checker utilizes two XOR gates each made of 2 inverters and 2 ambipolar transistors; hence, it has a hybrid nature.
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