A Just-In-Time Modulo Scheduling for Virtual Coarse-Grained Reconfigurable Architectures

Provided by: Institute of Electrical & Electronic Engineers
Topic: Hardware
Format: PDF
In the past decade, most solutions concerning the mapping of the compute-intensive loop kernels to accelerators have used heuristics and compiler-based strategies. These facts require that most of the decisions be taken at design time, thus precluding efficient solutions that can take run-time information into account. Any success in accelerating such applications greatly depends on two steps, extracting the loops and mapping them into the architecture. This last step is a challenge in itself since it is a NP-complete problem.

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