Binary Information Press
Circuit partition is an important part in VLSI design and it directly impacts on the overall performance of the circuit. This paper presents an algorithm based on the signal delay, named KKTBA. The Karush-Kuhn-Tucker (KKT) theorem is used to solve the signal delay optimization problem under the FPGA pins and logic capacity constraints and get interconnect relationship among elements under the limitations. Get the new associated matrix by solving the KKT equations, while using the Markov process to obtain the partition results.