A Light-Weight Fairness Mechanism for Chip Multiprocessor Memory Systems

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Provided by: Association for Computing Machinery
Topic: Hardware
Format: PDF
Chip Multi-Processor (CMP) memory systems suffer from the effects of destructive thread interference. This interference reduces performance predictability because it depends heavily on the memory access pattern and intensity of the co-scheduled threads. In this paper, the authors confirm that all shared units must be thread-aware in order to provide memory system fairness. However, the current proposals for fair memory systems are complex as they require an interference measurement mechanism and a fairness enforcement policy for all hardware-controlled shared units. Furthermore, they often sacrifice system throughput to reach their fairness goals which is not desirable in all systems.
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