A Literature Review on Leakage and Power Reduction Techniques in CMOS VLSI Design
A rapid growth in semiconductor technology and increasing demand for portable devices powered up by battery has led the manufacturers to scale down the feature size, resulting reduced threshold voltage and thereby enabling integration of extremely complex functionality on a single chip. In CMOS circuits, increased sub-threshold leakage current refers static power dissipation is the result of low threshold voltage. For the most recent CMOS technologies static power dissipation i.e. leakage power dissipation has become a challenging area for VLSI chip designers.