A Low Area and Low Power Programmable Baseband Processor Architecture
Fully programmable radio baseband processor architecture is presented. The architecture is based on a DSP processor core and a number flexible accelerator, connected via a configurable network. Design choices are motivated by the inherent properties of the baseband algorithms used in different types of radio systems. A large degree of hardware reuse between algorithms and standards, careful selection of accelerators, and low memory cost allows very area and power efficient implementation of multi-standard radio baseband processors.