A Low-Area Yet Performant FPGA Implementation of Shabal

In this paper, the authors present an efficient FPGA (Field Programmable Gate Array) implementation of the SHA-3 hash function candidate Shabal. Targeted at the recent Xilinx Virtex-5 FPGA family, their design achieves a relatively high throughput of 2 Gbit/s at a cost of only 153 slices, yielding a throughput-vs-area ratio of 13.4 Mbit/s per slice. Their work can also be ported to Xilinx Spartan-3 FPGAs, on which it supports a throughput of 800 Mbit/s for only 499 slices, or equivalently 1.6 Mbit/s per slice.

Provided by: LORIA Topic: Hardware Date Added: Mar 2011 Format: PDF

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