A Low Complexity Heuristic for Design of Custom Network-on-Chip Architectures

Provided by: edaa
Topic: Hardware
Format: PDF
Network-on-Chip (NoC) has been proposed to replace traditional bus based architectures to address the global communication challenges in nanoscale technologies. In future SoC architectures, minimizing power consumption will continue to be an important design goal. In this paper, the authors present a novel heuristic technique consisting of system-level physical design, and interconnection network generation that generates custom low power NoC architectures for application specific SoC. Their demonstrate the quality of the solutions produced by their technique by experimentation with many benchmarks.

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