A Low-Cost Methodology for Soft Error Free Logic Circuits

Provided by: International Journal of Engineering Trends and Technology
Topic: Hardware
Format: PDF
Continuous scaling of the transistor size and reduction of the operating voltage has led to a significant performance improvement of integrated circuits. However, the vulnerability of the scaled circuits to transient data upsets or soft errors, which are caused by alpha particles and cosmic neutrons, has emerged as a major reliability concern. In this paper, the authors have investigated the effects of soft errors in combinational circuits and proposed soft error detection techniques for high speed adders. In particular, they have proposed an area-efficient 64-bit Soft error Robust logarithmic Adder (SRA).

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