A Low-Cost SEE Mitigation Solution for Soft-Processors Embedded in Systems On Programmable Chips

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Provided by: edaa
Topic: Hardware
Format: PDF
The availability of multimillion Commercial-Off-The-Shelf (COTS) Field Programmable Gate Arrays (FPGAs) is making now possible the implementation on a single device of complex systems embedding processor cores as well as huge memories and ad-hoc hardware accelerators exploiting the programmable logic (System-on-Programmable-Chips (SoPCs)). When deployed in safety- or mission-critical applications, as avionic- and space-oriented ones, Singe Event Effects (SEEs) affecting COTS FPGA, which may have catastrophic effects if neglected, have to be considered and SEE mitigation techniques have to be employed.
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