A Low Latency Wormhole Router for Asynchronous On-Chip Networks

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Provided by: University of Malta
Topic: Hardware
Format: PDF
Asynchronous on-chip networks are power efficient and tolerant to process variation but they are slower than synchronous on-chip networks. A low latency asynchronous wormhole router is proposed using sliced sub-channels and the look-ahead pipeline. Channel slicing removes the C-element tree in the completion detection circuit and convert a channel into multiple independent sub-channels reducing the cycle period. The look-ahead pipeline uses the early evaluation protocol to reduce cycle period. Using the look-ahead pipeline on the pipeline stages with the maximal cycle period improves the overall throughput.
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