A Low-Leakage Current Power 45-nm CMOS SRAM

The authors fabricated 1K-b SRAMs with a leakage current reduction circuit using a 45nm CMOS process. The measured stand-by leakage power of the 1K-b SRAM memory cell array significantly decreased to 5.4% that of the conventional SRAM memory cell array, while the speed degradation and area overhead were negligible and the "Write" operating margin was increased. They concluded that the developed SRAM incorporating the SVL circuit, which can retain data even in stand-by, will play a major role in future deep sub-100nm CMOS SRAMs.

Provided by: Creative Commons Topic: Hardware Date Added: Apr 2011 Format: PDF

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