A Low-Overhead Asynchronous Interconnection Network for GALS Chip Multiprocessors
A new asynchronous interconnection network is introduced for Globally-Asynchronous Locally-Synchronous (GALS) chip multiprocessors. The network eliminates the need for global clock distribution, and can interface multiple synchronous timing domains operating at unrelated clock rates. In particular, two new highly-concurrent asynchronous components are introduced which provide simple routing and arbitration/merge functions. Post-layout simulations in identical commercial 90nm technology indicate that comparable recent synchronous router nodes have 5.6-10.7x more energy per packet and 2.8- 6.4x greater area than the new asynchronous nodes.