International Journal for Innovative Research in Science and Technology (IJIRST)
A low power 1MHz full programmable frequency divider in 45-nm CMOS process is presented in this paper. The divide ratio can be varied from 2400 to 2431 in a step size of 1. The divider consists of a divide-by-2 circuit, divide-by-2/3 prescaler, divide-by-32/33 prescaler, a programmable pulse-swallow counter. The post simulation results demonstrate that the divider can operate with the input frequency ranging from 2.46GHz-2.541GHz. Measured results show that programmable divider consuming only 613.39uW at 1V power supply.