A Low Power 50 nm Technology Based CMOS Inverter with Sleep Transistor Scheme

In this paper, the authors propose a sleep transistor based minimum size inverter in BSIM 4.3.0, 50nm CMOS technology with supply voltage of 1V, power dissipation of 46.28nW at 0.502V and maximum drain current of 70nA. The operating frequency is 1GHz. The disadvantage is decrease in voltage swing by 15% compared to the conventional CMOS Inverter of the same size, whereas the power dissipation is only 1.117% of the power dissipated by classical CMOS inverter and operating frequency is almost 2 times.

Provided by: International Journal of Computer Science & Engineering Technology (IJCSET) Topic: Hardware Date Added: Oct 2011 Format: PDF

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