A Low-Power Architecture for Maximum a Posteriori Decoding
In this paper, the authors present a novel architecture for Soft-Input Soft-Output (SISO) Maximum A Posteriori (MAP) decoding. The architecture leverages an ASIP (Application Specific Instruction-set Processor) structure, where the datapath has been designed to achieve high-speed performance and low power dissipation. Salient features of this architecture include: delayed renormalization of the metrics with register by-passing to reduce latency, use of register files to minimize power dissipation and micro-programmed control to achieve flexibility. The resulting architecture for the SISO-MAP decoder achieves a maximum throughput of 10.9 Msymbols/second, operating at 142MHz and dissipating 21mW in the datapath.