A Low Power Area Efficient Design for 1-Bit Full Adder Cell

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Provided by: International Journal of Computer Science and Information Technologies
Topic: Hardware
Format: PDF
The demand and popularity of the portable electronics is driving the designers towards smaller silicon area, lesser power consumption and lesser delay. In this paper, the authors present a 1 bit full adder cell. It was implemented with lesser number of transistors and lesser power consumption compared to the existing implementations of the full adder. Simulations are carried for supply voltages of 1.2v, 0.8v in HSPICE at 0.18umCMOS technology. Proposed full adder results show that there was a reduction of power consumption and efficient in area. Area was measured using micro wind tool.
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