A Low Power CMOS Voltage Mode SRAM Cell for High Speed VLSI Design
In this paper, the authors propose a novel design of a low power Static Random Access Memory (SRAM) cell for high speed operations. The model adopts the voltage mode method for reducing the voltage swing during the write operation switching activity. Dynamic power dissipation increases when the operating frequency of the SRAM cell increases. In the proposed design they use two voltage sources connected with the bit line and Bit bar line for reducing the voltage swing during the write "0" or write "1" operation. They use 90 nm CMOS technology with 1 volt of power supply. Simulation is done in Microwind 3.1 by using BSim4 model.