A Low Power Comparator Design for 6-Bit Flash ADC in 90-nm CMOS

In this paper, the authors design a "Low power flash ADC" for ultra-wide band applications using CMOS 90nm technology. Flash ADC consists of a reference generator, array of comparators, 1-out-of N code generator, fat tree encoder and output D latches. The demanding issues in the design of a low power flash ADC is the design of low power latched comparator. The proposed comparator in this paper, is designed using 90nm technology at 0.8V DC voltage source using H SPICE tool. The simulation results of a 6-bit flash ADC is shown for a sampling frequency up to 1.2GHz showing an average power dissipation of 7.67mW.

Provided by: International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering (IJAREEIE) Topic: Hardware Date Added: Jun 2014 Format: PDF

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