A Low-Power High-Speed Pipelined Accumulator Design Using CMOS Logic for DSP Applications

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Provided by: Academicians Research Center (ARC)
Topic: Hardware
Format: PDF
The pipelined accumulator forms the basic building block of arithmetic modules for DSP applications. The basic building block of an accumulator unit is the adder cell and data storage registers e.g. Flip-Flop (FF). The operational speed of FF determines the correctness and accuracy of the functionality of 12BDA. The high-speed full adders that use low power consumption is a fundamental arithmetic operation that can never be neglected in accumulator unit, and it is one of the speed-limiting elements. The efficiency of the accumulator unit is determined by the adder cell taken in to account.
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