University of Texas at Arlington
All other things being equal, hardware specialized for a specific application will outperform hardware that has not been specialized for that specific application. Special-purpose hardware can dramatically accelerate an application. However, designing special-purpose hardware is often prohibitively expensive in terms of manpower and time. This paper describes a methodology that uses reconfigurability to enable the efficient compilation of a class of domain specific languages. The authors present the methodology, a prototype compiler, and a 40 Gb/sec network processor designed to be implemented on an FPGA using that compiler.